www.siliconstandard.com 1 of 5 n-channel enhancement-mode power mosfet simple drive requirement bv dss 60v lower gate charge r ds(on) 40mw fast switching characteristics i d 6.9a description absolute maximum ratings advanced power mosfets from silicon standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. the SSM9475M is in the so-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well suited for low voltage applications such as dc/dc converters. s s s g d d d d so-8 g d s symbol units v ds v v gs v i d @ t a =25c i d @ t a =100c i dm a p d @ t a =25c w/c t stg t j symbol value unit rthj-a thermal resistance junction-ambient 3 max. 50 c/w rating 60 6.9 a parameter drain-source voltage gate-source voltage continuous drain current 3 continuous drain current 3 5.5 a pulsed drain current 1 30 2.5 w -55 to 150 c operating junction temperature range -55 to 150 c linear derating factor 0.02 storage temperature range parameter total power dissipation 25 SSM9475M thermal data 3/21/2005 rev.2.01
www.siliconstandard.com 2 of 5 3/21/2005 rev.2.01 symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =1ma 60 - - v d bv dss / d t j breakdown voltage temperature coefficient reference to 25 c, i d =1ma - 0.073 - v/c r ds(on) static drain-source on-resistance 2 v gs =10v, i d =6a - - 40 mw v gs =4.5v, i d =4a - - 50 mw v gs(th) gate threshold voltage v ds =v gs , i d =250ua 1 - 3 v g fs forward transconductance v ds =10v, i d =6a - 10 - s i dss drain-source leakage current (t j =25 o c) v ds =60v, v gs =0v - - 1 ua drain-source leakage current (t j =70 o c) v ds =48v, v gs =0v - - 25 ua i gss gate-source leakage v gs =25v - - 100 na q g total gate charge 2 i d =6a - 19 30 nc q gs gate-source charge v ds =48v - 5 - nc q gd gate-drain ("miller") charge v gs =4.5v - 10 - nc t d(on) turn-on delay time 2 v ds =30v - 11 - ns t r rise time i d =1a - 6 - ns t d(off) turn-off delay time r g =3.3w ,v gs =10v - 35 - ns t f fall time r d =30w -1 0- ns c iss input capacitance v gs =0v - 1670 2670 pf c oss output capacitance v ds =25v - 160 - pf c rss reverse transfer capacitance f=1.0mhz - 116 - pf r g gate resistance f=1.0mhz - 1.58 - w symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =2a, v gs =0v - - 1.2 v t rr reverse recovery time i s =6a, v gs =0 v , - 34 - ns q rr reverse recovery charge di/dt=100a/s - 50 - nc notes: 1.pulse width limited by max. junction temperature. 2.pulse width < 300us , duty cycle < 2%. 3.surface mounted on 1 in 2 copper pad of fr4 board ; 125c/w when mounted on min. copper pad. ss m 9 4 7 5 m electrical characteristics @ t = 25 c (unless otherwise specified) j o source-drain diode
www.siliconstandard.com 3 of 5 fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0 20 40 60 80 100 0123456 v ds , drain-to-source voltage (v) i d , drain current (a) t a =25 o c 10v 6.0v 5.0v 4.5v v g =3.0v 0 10 20 30 40 50 60 70 80 0123456 v ds , drain-to-source voltage (v) i d , drain current (a) 10v 6.0v 5.0v 4.5v v g =3.0v t a = 150 o c 32 34 36 38 40 42 44 46 35791 1 v gs , gate-to-source voltage (v) r ds(on) (mw ) i d =4a t a =25c 0.6 0.8 1.0 1.2 1.4 1.6 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d =6a v g =10v 0.50 0.75 1.00 1.25 1.50 -50 0 50 100 150 t j , junction temperature ( o c) normalized v gs(th) (v) 0 1 2 3 4 5 6 0 0.2 0.4 0.6 0.8 1 1.2 v sd , source-to-drain voltage (v) i s (a) t j =25 o c t j =150 o c ss m 9 4 7 5 m 3/21/2005 rev.2.01
www.siliconstandard.com 4 of 5 fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 4.5v q gs q gd q g charge 100 1000 10000 1 5 9 1 31 72 12 52 9 v ds , drain-to-source voltage (v) c (pf) f =1.0mhz c iss c oss c rss 0 2 4 6 8 10 12 14 0 1 02 03 04 05 0 q g , total gate charge (nc) v gs , gate to so ur ce voltage (v) v ds =30v v ds =38v v ds =48v i d =6a 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) p dm duty factor = t/t peak t j = p dm x r thja + t a r thja = 125c/w t t 0.02 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse 0.01 0.1 1 10 100 0.1 1 10 100 1000 v ds , drain-to-source voltage (v) i d (a) 1ms 10ms 100ms 1s dc t a =25 o c single pulse ss m 9 4 7 5 m 3/21/2005 rev.2.01
in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 5 of 5 ss m 9 4 7 5 m 3/21/2005 rev.2.01
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